Evidence map›Paper›PMID 42850269›Full record

ArticleNature communications2026

Two-dimensional digital-analog multimode circuits based on asymmetric vertical double-gate WSe

Weijia Tian, Xiaofu Wei, Hang Zhao, Zhihong Cao, Yanzhe Zhang, Zhangyi Chen, Yan Zhou, Wei ShangGuan, Xiankun Zhang, Zheng Zhang and 1 more

Abstract read
PubMed Publisher
In one paragraph

Article in Nature communications, 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.

0numbers the graph read from it
0cells of the map it votes in
0citing papers in PubMed
–field-weighted citation impact
1 · What the graph read from it

What it found

Each row is one number read from the abstract, on the scale the paper reported it, with its interval. Left of the dashed line favours the treatment, right favours the comparator. Under each row is the sentence it came from. New to these charts? A ten-minute tutorial.

The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.

2 · The registry

The trial behind it

Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.

Neither the registry nor the abstract names a trial number. If this is a trial report, that itself is worth knowing.

3 · Its place in the literature

Who cites it

0 citing papers in PubMed.

No citing paper in PubMed yet.

4 · The record

Corrections and comments

PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.

5 · Who and what money

Authors and funding

11 authors.

Weijia Tian *Academy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China.
Xiaofu Wei *Academy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China.
Hang ZhaoAcademy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China.
Zhihong CaoAcademy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China.
Yanzhe ZhangAcademy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China.
Zhangyi ChenAcademy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China.
Yan ZhouAcademy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China.
Wei ShangGuanAcademy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China.
Xiankun ZhangAcademy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China. zhangxiankun@ustb.edu.cn.ORCID http://orcid.org/0000-0001-9654-4659
Zheng ZhangAcademy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China. zhangzheng@ustb.edu.cn.ORCID http://orcid.org/0000-0002-9104-7562
Yue ZhangAcademy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, P. R. China. yuezhang@ustb.edu.cn.ORCID http://orcid.org/0000-0002-8213-1420

Funding

China Postdoctoral Science Foundation 2025M780018National Science Foundation of China | National Natural Science Foundation of China-Yunnan Joint Fund (NSFC-Yunnan Joint Fund) 52188101, 55052225206, 62322402, 52350301, 92463308, 62504018Natural Science Foundation of Beijing Municipality (Beijing Natural Science Foundation) JQ26010
6 · The paper itself

Abstract

Digital-analog multimode operation constitutes a critical enabling technology for next-generation integrated circuits, delivering the performance and multifunctionality necessary to fulfill dynamic system requirements. However, implementing such operation in a single circuit faces a substantial challenge, owing to the fundamentally distinct requirements on carrier transport behavior of transistors. Here, we report an asymmetric vertical double-gate (AVDG) device architecture designed to achieve digital-analog multimode operation. Specifically, the AVDG transistor combines an asymmetric source-drain configuration with dual air-gaps for barrier broadening and metal shielding, allowing the drain-source bias to serve as an additional control terminal. This design enables coordinated modulation of the channel carrier polarity and source-drain injection barriers, allowing the device to be programmed into multiple carrier-transport states. These diverse field-effect characteristics enable the realization of reconfigurable multifunctional logic and analog operations with the combined programming of dual-gate voltages and drain-source bias. With a same circuit unit composed of two AVDG transistors, we demonstrate seven digital logic functions and six analog signal-processing functions. These functions exhibit a good rail to rail logic operation, which suggests that the units could be cascaded to create complex circuits.

Identifiers

What OpenQuestion holds

Textmetadata
Read underepoch 390

Registered trials

None linked

Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.