ArticleNature communications2026
Gate-level three-dimensional integration of two-dimensional logic cells.
Article in Nature communications, 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
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Authors and funding
11 authors.
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Abstract
Monolithic three-dimensional (M3D) integration is a promising strategy to increase logic density within a limited footprint. Conventional M3D circuits rely on transistor-level partitioning, in which logic functions are constructed through interconnections among numerous transistors across different tiers, limiting circuit compactness. Here, we propose a gate-level M3D integration architecture based on two-dimensional (2D) logic cells (LCs), in which the basic interlayer connection unit is shifted from an individual transistor to a logic gate. Through multidimensional modulation of carrier transport in the WSe
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