ArticleMicromachines2026
Hardware-Algorithm Co-Optimization of Weight-Update Protocols in Oxide-Based Synaptic Transistor Arrays for Neuromorphic Systems.
Article in Micromachines, 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
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Abstract
The transition from single-device characterization to array-level simulation remains a critical challenge in the development of three-terminal synaptic transistors for neuromorphic computing, as most existing simulation studies either extract parameters from a single representative device and apply them uniformly, or rely on weight-update strategies originally designed for two-terminal memristors. Here, we establish an experimentally calibrated behavioral simulation framework based on differential conductance-pair mapping (W = G
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