ReviewMicromachines2026
Research on Memristors in Hardware Security.
Review in Micromachines, 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
What it found
Each row is one number read from the abstract, on the scale the paper reported it, with its interval. Left of the dashed line favours the treatment, right favours the comparator. Under each row is the sentence it came from. New to these charts? A ten-minute tutorial.
The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
The trial behind it
Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.
Neither the registry nor the abstract names a trial number. If this is a trial report, that itself is worth knowing.
Who cites it
0 citing papers in PubMed.
No citing paper in PubMed yet.
Corrections and comments
PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.
Authors and funding
8 authors.
Funding
Abstract
As the deep integration of the Internet of Things (IoT) and artificial intelligence (AI) technologies has rendered traditional encryption techniques increasingly inadequate in terms of security strength, the implementation of hardware-level security solutions has been identified as a critical issue in the design of information systems. Memristors, as passive circuit components with their intrinsic stochastic switching behavior, multistate storage capability, and low power consumption, have been exploited to provide a viable approach for the construction of hardware security primitives, including true random number generators (TRNGs) and physically unclonable functions (PUFs). In this review, the latest research advances in memristor-based hardware security technologies were systematically surveyed from three perspectives, namely TRNGs, PUFs and other security schemes. With regard to TRNGs and PUFs, respectively, we have systematically summarized their characteristics, including throughput, power consumption and randomness quality, as well as uniqueness, reliability and methods, with particular attention paid to the types of entropy sources and bit-generation strategies. In addition, the potential application of other memristor-based hardware security solutions in information hiding, encrypted transmission and authentication was also analyzed. Subsequently, the principal challenges impeding the transition from laboratory research to mass production were summarized, encompassing synergistic integration with advanced CMOS processes, the balance between reliability and stochasticity, and the absence of design methodologies that integrate hardware and software. Future development trajectories were further delineated, including cross-layer optimization across devices, circuits, and systems, the design of high-security chips resistant to machine learning attacks, CMOS-compatible stable implementation schemes, and the on-chip integration of TRNGs, PUFs, and encryption engines. The present review is intended to serve as a systematic reference for the design of novel hardware security systems, thereby paving the way for the practical deployment of memristor-based security technologies.
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Registered trials
Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.