Correlation Between Geometric Parameters and Capacitance in Silicon Detectors: A Study Based on Physical Modeling, Simulation, and Experiment.

This study proposes and validates a unified geometry-based capacitance model for four representative silicon detector architectures: planar, 3D trench electrode, 3D spherical electrode, and silicon drift detector (SDD). Closed-form analytical expressions explicitly relate capacitance to key geometric parameters-anode radius, depletion thickness, electrode depth, and electrode spacing-and the resulting geometric scaling laws are rigorously verified by combining physical modeling, TCAD simulation, and experimental measurement. A central finding is that for highly symmetric structures, capacitance is governed almost exclusively by the radius of the collecting anode and is essentially independent of the overall detector volume, thereby defining an ideal low-capacitance limit. For the SDD, a hemispherical capacitor approximation accurately captures this anode-dominated behavior, and measurements on prototypes together with independent literature data confirm that the total capacitance can be decomposed into an intrinsic geometric component and a parasitic contribution. This work provides a unified framework and direct cross-structure design guidelines for minimizing capacitance toward ultra-low-noise, high-performance silicon detectors.