Defect-mediated generation-recombination dynamics governing conductance response in floating-body transistors.

As CMOS technologies evolve toward ultra-thin floating-body architectures, defect-mediated carrier dynamics increasingly dominate device behavior, challenging conventional linear interpretations of electrical response in nanoscale transistors. In this work, we demonstrate that the conductance response of foundry-fabricated floating-body transistors is governed by generation-recombination (GR) dynamics associated with deep-level defects inside the ultra-thin silicon body. Frequency-dependent conductance measurements reveal bell-shaped responses that exhibit weak gate-bias dependence but strong temperature sensitivity, deviating fundamentally from conventional interface-trap-dominated behavior observed in bulk MOSFETs. By correlating conductance analysis with temperature-dependent low-frequency noise spectroscopy, we identify a common dynamical origin of both phenomena and extract the energetic position and density of channel defects. The conductance peak dynamics follow thermally activated GR processes, indicating that the measured admittance reflects a complex interaction between inversion carriers and channel defects under volume-inversion conditions. Furthermore, electrical stress induces a bias-dependent transition in the dominant conductance mechanism, revealing a crossover from interface-controlled to channel-defect-controlled dynamics. These findings indicate that conductance measurements in ultra-thin floating-body transistors probe a coupled defect system, providing a physically grounded framework for interpreting conductance and noise dynamics in advanced nanoscale electronic devices.