An integrated framework TSV-INet for arbitrarily distributed TSV interposer wafer warpage simulation.

Through-silicon vias (TSVs) are densely integrated in TSV interposer wafers, and TSV-induced warpage can degrade downstream manufacturing yield. Fast, accurate design-stage warpage simulation is therefore essential. This study presents TSV-INet, a hybrid framework that combines a convolutional neural network and a graph neural network to predict the anisotropic effective properties of TSV representative volume elements (RVEs) and enable wafer-level warpage simulation through RVE-based finite element homogenization. By combining pixel-level material-field encoding with topology-aware message passing on TSV layout graphs, TSV-INet improves data efficiency and robustness to previously unseen layouts relative to CNN-only baselines. Using this framework, we further examine the effects of TSV layout and density on wafer-level thermo-mechanical behavior. For non-extreme layouts with identical TSV count, layout redistribution has only a limited influence on global warpage, but it substantially affects local stress concentration within the interposer die. By contrast, increasing TSV density markedly amplifies wafer warpage and promotes the transition from bowl-like to saddle-like deformation. These findings provide practical guidance for warpage-aware and stress-aware TSV interposer design.