A Backside-Electrode-Free Lateral 4H-SiC JFET with Three-Terminal Dual-Gate Design for Stable DC Operation at 500 °C.

To address the urgent need for electronics operable in extremely high-temperature environments, this paper presents a novel three-terminal, dual-gate, lateral 4H-SiC n-channel depletion-mode junction field effect transistor (JFET) without a backside electrode. Featuring a fully planar electrode layout, the device eliminates the back-gate effect and significantly improves integration compatibility. Experimental results demonstrate stable DC operation up to 500 °C, with an intrinsic gain of 9.79 at room temperature and 6.01 at 500 °C. Comparison with TCAD simulations confirms excellent agreement in the key physical trends of threshold voltage drift and mobility degradation, though quantitative discrepancies are observed and attributed to process-induced parasitic effects such as non-ideal ohmic contacts and interface states. Analysis shows that the new structure broadens the channel depletion layer by optimizing the depletion profile, thereby suppressing channel-length modulation and improving both output resistance and gate control. This work not only provides an effective device platform for high-temperature 4H-SiC analog integrated circuits (ICs) but also deepens the understanding of process-performance correlations, offering clear guidance for process-oriented device optimization. The proposed structure serves as a foundation for developing fully planar, high-temperature 4H-SiC analog ICs with promising potential in aerospace, automotive, and energy exploration systems.