ArticleiScience2026
System-level FPGA validation of a trainable and robust multiplier-free spiking neural network.
Article in iScience, 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
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2 authors.
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Abstract
The growing scale of artificial intelligence models has expanded their impact, yet efficient deployment on hardware remains challenging due to intensive matrix-based computation and energy demand. Spiking neural networks (SNNs), inspired by biological neural processing, offer an event-driven and energy-efficient alternative for neuromorphic computing. In this work, we present a system-level FPGA validation of a trainable, multiplier-free SNN that supports on-chip supervised learning under fixed-point constraints. By implementing a sensitive-noise threshold (SNT) mechanism and a limited remote supervised method (LReSuMe) on a Xilinx ZCU104 FPGA platform, the proposed design achieves high throughput, low power consumption, and preserved robustness to the noise. Weight visualization further indicates structured and interpretable learning behavior, supporting the reliability of hardware-based neuromorphic systems.
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Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.