A fully-CMOS spiking LIF neuron implementation for optimized STDP learning on memristor.

The growing demand for fast and energy-efficient computing has motivated the development of neuromorphic hardware inspired by biological neural systems. Spiking neural networks (SNNs), as the third generation of neural networks, offer an event-driven and highly parallel computing paradigm that is well suited for such applications. A key challenge in hardware SNNs is the efficient implementation of synaptic learning mechanisms, particularly spike-timing-dependent plasticity (STDP), with minimal circuit complexity and energy overhead. In this work, we propose a fully CMOS leaky integrate-and-fire (LIF) neuron designed to enable local, on-chip STDP-like learning when interfaced with analog memristive synapses. The proposed neuron generates a bipolar output spike composed of both positive and negative voltage pulses, allowing direct modulation of memristor conductance without the need for complex peripheral circuits or explicit timing storage elements. The neuron operates in two distinct modes of training mode, which produces bipolar spikes to support synaptic updates, and inference mode, which generates a single unipolar spike while deactivating non-essential circuitry to reduce power consumption. To validate the proposed design, a proof-of-concept 15×4 spiking neural network incorporating a winner-takes-all (WTA) mechanism is implemented in 65-nm CMOS technology and evaluated using circuit-level simulations. The results demonstrate correct local synaptic adaptation, stable neuron operation under process variations, and successful pattern association during training and inference. The network processes each training pattern within 0.6 ms and performs inference within 0.32 ms.