An Energy-Efficient LiDAR Receiver Using Time-to-Voltage Converter and SAR ADC in 180 nm CMOS.

This paper proposes an energy-efficient LiDAR receiver topology based on a time-to-voltage converter (TVC) followed by a 5-bit SAR ADC. By converting the time-interval between START and STOP signals into the voltage domain, the proposed topology avoids the complexity of conventional TDC-based designs and enables the use of a moderate-speed, energy-efficient SAR ADC. The proposed TVC in the proposed LiDAR receiver consists of an on-chip avalanche photodiode (APD), a CMOS transimpedance-limiting amplifier (CTLA), a time-gating circuit, a ramp generator, and a peak-and-hold (PDH) block. Thereafter, the converted voltages are digitized by a VCM-based single-ended SAR ADC with a binary-weighted CDAC, a strong-arm latch comparator, and custom digital logic. A reset generator is also incorporated to coordinate the sampling, comparison, and settling phases. The proposed LiDAR receiver is implemented in a 180 nm CMOS process, where the TVC occupies an area of 171 μm × 98.8 μm, while the TVC-SAR receiver occupies 417 μm × 356 μm, respectively. The proposed LiDAR receiver consumes 13 mW from a single 1.8 V supply, in which the SAR ADC consumes 3.68 mW only. The TVC-SAR receiver resolves the time-intervals ranging from 7 ns to 32.1 ns with a resolution of 0.81 ns. Hence, the proposed topology provides an energy-efficient solution along with its reduced circuit complexity and chip implementation for short-range LiDAR applications.