A unified performance-cost landscape of parallel p-bit Ising machines based on update dynamics.

Parallel p-bit Ising machines provide a promising hardware platform for fast and energy-efficient combinatorial optimization, but their scalability and efficiency critically depend on update synchronization, hardware timing, and architectural cost. Here we develop a unified performance–cost landscape for parallel p-bit annealing by systematically analyzing synchronous and asynchronous update schemes under realistic constraints, including finite hardware delay, time-multiplexed p-bit reuse, and limited input digital-to-analog (DAC) precision. We show that synchronous updates are not inherently unstable, but can suffer from oscillations when excessive update simultaneity is present, while asynchronous updates are structurally constrained by hardware delay and require slower operation to maintain stability. To bridge performance and hardware efficiency, we introduce time-multiplexed reuse of physical p-bits combined with structured synchronous control policies, which preserve statistically valid annealing dynamics while reducing the effective update rate. This reuse decouples statistical correctness from physical resource count, enabling the number of physical p-bits and input DACs to scale approximately as the inverse of the time-multiplexing reuse factor. As a result, synchronous architectures access low-cost operating regimes, achieving comparable or superior solution quality at less than half the normalized hardware cost of optimized asynchronous updates on G-set MaxCut benchmarks with 800–2000 nodes under matched annealing time. We further demonstrate that low-resolution input DACs (typically 3–4 bits) are often sufficient to achieve performance within a few percent of the best-known solutions (normalized cut values [Formula: see text]) when annealing time is appropriately adjusted. Together, these results establish coordinated time-multiplexed p-bit reuse combined with structured synchronous control as a key architectural principle for scalable probabilistic computing hardware, and provide reproducible design guidance for balancing solution quality, hardware cost, and timing constraints under realistic delay and precision limitations.