ArticleSensors (Basel, Switzerland)2026
Comprehensive Comparison of Front- and Back-Illuminated Single-Photon Avalanche Diodes in 110 nm Standard CMOS Image Sensor Technology.
Article in Sensors (Basel, Switzerland), 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 1 paper.
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1 citing paper in PubMed.
- Developing the Readout Electronics for a Custom 64 × 64 SPAD Array: From Single-Board Prototyping to FPGA Implementation Toward Stellar Intensity Interferometry.Sensors (Basel, Switzerland) · 2026Article
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7 authors.
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Abstract
This paper presents a process-controlled study of illumination engineering in single-photon avalanche diodes (SPADs) fabricated in a 110 nm standard CMOS image sensor (CIS) technology. Front-illuminated (FI) and back-illuminated (BI) SPADs were implemented with identical front-end-of-line (FEOL) structures, including the junction and guard-ring configurations, enabling the isolation of the effects of illumination direction and back-end-of-line (BEOL) configuration without modifying the junction structure. Through TCAD simulations and comprehensive experimental characterizations, including current-voltage, light-emission, dark count rate (DCR), photon detection probability (PDP), and timing-jitter measurements, we systematically analyze the performance trade-offs introduced by the BI configuration. The BI SPAD exhibits enhanced near-infrared PDP and a broader spectral response due to its deeper absorption region and the incorporation of a metal reflector, while maintaining identical avalanche characteristics, as evidenced by an unchanged 72 ps full-width-at-half-maximum (FWHM) timing jitter. However, the backside illumination increases the diffusion tail, indicating a trade-off between near-infrared sensitivity and diffusion-related timing performance. These results provide design guidelines for optimizing SPAD performance through illumination-direction and BEOL engineering while preserving the FEOL design and demonstrate a useful approach for SPAD integration in standard CMOS technology.
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