ArticleNanoscale advances2026
Raised or recessed? Finding the optimal gate architecture for improving the static performance of graphene transistors.
Article in Nanoscale advances, 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
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5 authors.
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Abstract
As silicon CMOS technology approaches its scaling limits, graphene offers a compelling alternative as the active material channel in transistors due to its high carrier mobility and atomically thin profile, which provide strong electrostatic control and promise high-performance analog applications. However, roadblocks such as device-to-device variation, high contact resistance, poor dielectric interfaces, and non-uniform graphene quality have limited the adoption of graphene field effect transistors (GFETs). Hence, further investigations are required for mitigating these issues at a material,
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