ArticleAdvanced science (Weinheim, Baden-Wurttemberg, Germany)2026
Dual-Modulated Vertically Stacked Transistors With Fully Laminated Plate-Type Architecture Featuring Nanoscale Channel Length.
Article in Advanced science (Weinheim, Baden-Wurttemberg, Germany), 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
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Abstract
A transistor with fully laminated plate-type triode electrodes, source, drain and gate offers higher current density than a typical transistor design by allowing a 2D current path. Nanoscale transistors face challenges like off-state leakage, so we introduce a new design using a laminated plate-type architecture and a dual-modulation strategy to improve performance and stability. Both top and bottom gates are used as active electrodes to fully control the channel's thickness. A micro-hole patterned electrode is employed to enable effective gate field penetration into the channel, while a graphene electrode facilitates Fermi-level modulation and improves field transfer. Furthermore, a leakage blocking layer is inserted to suppress unwanted carrier injection in the source and drain overlap regions. The device achieves low off-state current of ≈10
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