Evidence map›Paper›PMID 41519952›Full record

ArticleNature communications2026

Pruning random resistive memory for optimizing analog AI.

Yi Li, Songqi Wang, Yaping Zhao, Shaocong Wang, Bo Wang, Woyu Zhang, Yangu He, Ning Lin, Binbin Cui, Xi Chen and 13 more

Abstract read
In one paragraph

Article in Nature communications, 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 3 papers.

0numbers the graph read from it
0cells of the map it votes in
3citing papers in PubMed
–field-weighted citation impact
1 · What the graph read from it

What it found

Each row is one number read from the abstract, on the scale the paper reported it, with its interval. Left of the dashed line favours the treatment, right favours the comparator. Under each row is the sentence it came from. New to these charts? A ten-minute tutorial.

The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.

2 · The registry

The trial behind it

Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.

Neither the registry nor the abstract names a trial number. If this is a trial report, that itself is worth knowing.

3 · Its place in the literature

Who cites it

3 citing papers in PubMed.

  1. A Dual-Programmable 2M NOR Flash Architecture for Energy-Efficient In-Memory Computing.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2026
    Article
  2. Article
  3. Review
4 · The record

Corrections and comments

PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.

5 · Who and what money

Authors and funding

23 authors.

Yi Li *Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.
Songqi Wang *Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.
Yaping ZhaoDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.
Shaocong WangDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.ORCID http://orcid.org/0000-0002-7195-8676
Bo WangDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.
Woyu ZhangResearch Center of Microelectronic Device and Integration Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China.
Yangu HeDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.ORCID http://orcid.org/0009-0008-9035-1686
Ning LinDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.ORCID http://orcid.org/0000-0002-6198-7043
Binbin CuiDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.
Xi ChenDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.
Shiming ZhangDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.ORCID http://orcid.org/0000-0002-9727-028X
Hao JiangFrontier Institute of Chip and System, Fudan University, Shanghai, China.
Peng LinCollege of Computer Science and Technology, Zhejiang University, Zhejiang, China.ORCID http://orcid.org/0000-0002-0679-8063
Xumeng ZhangFrontier Institute of Chip and System, Fudan University, Shanghai, China.ORCID http://orcid.org/0000-0002-3828-151X
Feng ZhangResearch Center of Microelectronic Device and Integration Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China.
Xiaojuan QiDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.ORCID http://orcid.org/0000-0002-4285-1626
Zhongrui WangSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, China. wangzr@sustech.edu.cn.ORCID http://orcid.org/0000-0003-2264-0677
Xiaoxin XuResearch Center of Microelectronic Device and Integration Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China. xuxiaoxin@ime.ac.cn.
Dashan ShangResearch Center of Microelectronic Device and Integration Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China. shangdashan@ime.ac.cn.ORCID http://orcid.org/0000-0003-3573-8390
Qi LiuResearch Center of Microelectronic Device and Integration Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China.ORCID http://orcid.org/0000-0001-7062-831X
Han WangDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China.ORCID http://orcid.org/0000-0001-5121-3362
Kwang-Ting ChengDepartment of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong, China.ORCID http://orcid.org/0000-0002-3885-4912
Ming LiuResearch Center of Microelectronic Device and Integration Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China.ORCID http://orcid.org/0009-0002-2570-7793

Funding

No grant is acknowledged in the PubMed record.

6 · The paper itself

Abstract

The rapid expansion of AI models has intensified concerns over energy consumption. Analog in-memory computing with resistive memory offers a promising, energy-efficient alternative, yet its practical deployment is hindered by programming challenges and device non-idealities. Here, we propose a software-hardware co-design that trains randomly weighted resistive-memory neural networks via edge-pruning topology optimization. Software-wise, we tailor the network topology to extract high-performing sub-networks without precise weight tuning, enhancing robustness to device variations and reducing programming overhead. Hardware-wise, we harness the intrinsic stochasticity of resistive-memory electroforming to generate large-scale, low-cost random weights. Implemented on a 40 nm resistive memory chip, our co-design yields accuracy improvements of 17.3% and 19.9% on Fashion-MNIST and Spoken Digit, respectively, and a 9.8% precision-recall AUC improvement on DRIVE, while reducing energy consumption by 78.3%, 67.9%, and 99.7%. We further demonstrate broad applicability across analog memory technologies and scalability to ResNet-50 on ImageNet-100.

Identifiers

PMID41519952
PMCPMC12858861

What OpenQuestion holds

Textmetadata
LicenceCC BY-NC-ND
Read underepoch 390

Registered trials

None linked

Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.