Evidence map›Paper›PMID 41357676›Full record

ArticleIEEE journal of solid-state circuits2025

A Scalable 1024-Channel Ultra-Low-Power Spike Sorting Chip with Event-Driven Detection and Spatial Clustering.

Arash Akhoundi, Pumiao Yan, Yawende Landbrug, Madeline Hays, Boris Murmann, E J Chichilnisky, Dante G Muratore

Abstract read
PubMed Full text at PMC Publisher
In one paragraph

Article in IEEE journal of solid-state circuits, 2025. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 3 papers.

0numbers the graph read from it
0cells of the map it votes in
3citing papers in PubMed
–field-weighted citation impact
1 · What the graph read from it

What it found

Each row is one number read from the abstract, on the scale the paper reported it, with its interval. Left of the dashed line favours the treatment, right favours the comparator. Under each row is the sentence it came from. New to these charts? A ten-minute tutorial.

The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.

2 · The registry

The trial behind it

Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.

Neither the registry nor the abstract names a trial number. If this is a trial report, that itself is worth knowing.

3 · Its place in the literature

Who cites it

3 citing papers in PubMed.

  1. Article
  2. A Framework for Compressive On-Chip Action Potential Recording.IEEE transactions on bio-medical engineering · 2026
    Article
  3. Article
4 · The record

Corrections and comments

PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.

5 · Who and what money

Authors and funding

7 authors.

Arash AkhoundiElectrical Engineering, University of Tehran, Sharif University of Technology; Department of Microelectronics, Delft University of Technology.
Pumiao YanElectrical and Computer Engineering, Cornell University; Electrical Engineering, Stanford University.
Yawende LandbrugBiomedical Engineering (TU Delft) and Neuroscience (Erasmus University Rotterdam); Erasmus MC, TU Delft and Stanford University.
Madeline HaysBioengineering-electrical engineering, Stanford Artificial Retina Project.
Boris MurmannCommunications engineering, Fachhochschule Dieburg, Dieburg, Germany; Electrical engineering, Santa Clara University, Santa Clara, CA, USA; Electrical engineering, University of California, Berkeley, CA, USA.
E J ChichilniskyNeurosurgery and Ophthalmology, Stanford University.
Dante G MuratoreElectrical Engineering, Politecnico of Torino; Microelectronics, Integrated Microsystems Laboratory, University of Pavia; Department of Microelectronics, Delft University of Technology.

Funding

Patterned Electrical Stimulation of the Retina for High-Resolution ProsthesesR01EY021271 · NEI · STANFORD UNIVERSITY · PI EDUARDO CHICHILNISKY · 2011 to 2026
$4.6M
Bi-directional neural interface for probing parallel visual pathwaysR01EY032900 · NEI · STANFORD UNIVERSITY · PI CHICHILNISKY, EDUARDO, COGAN, STUART F · 2021 to 2024
$2.8M
NEI NIH HHS R01 EY021271NEI NIH HHS R01 EY032900
6 · The paper itself

Abstract

This paper presents a 1024-channel ultra-low-power spike sorting chip featuring event-driven spike detection and spatial clustering for large-scale neural recording. To address power and scalability constraints in brain-computer interfaces, the design integrates a compressive ADC with a two-stage spike detector that significantly reduces memory and processing activity. Spatial features derived from high-density microelectrode array (MEA) enhance cluster separability, enabling robust performance even under neural signal distortion or probe drift, particularly when recordings are obtained using planar MEAs. A modified self-organizing map algorithm clusters spikes in the spatial domain with minimal memory access, supporting on-chip training and real-time operation with low latency. Fabricated in 40 nm CMOS, the chip achieves 0.00029 mm

Indexed as

Brain-computer interfacesevent-driven spike detectionhigh-density neural interfaceneural signal compressionneural signal processoron-chip spike sorting

Identifiers

PMID41357676
PMCPMC12680097

What OpenQuestion holds

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Registered trials

None linked

Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.