Evidence map›Paper›PMID 41287258›Full record

ArticleAdvanced materials (Deerfield Beach, Fla.)2026

Vertical Self-Rectifying Memristive Arrays for Page-Wise Parallel Logic and Arithmetic Processing.

Kunhee Son, Jea Min Cho, Dong Hoon Shin, Yeong Rok Kim, Néstor Ghenzi, Sunwoo Cheong, Byeong Su Kim, Jung Kyu Lee, Sungho Kim, Wonho Choi and 3 more

Abstract read
PubMed Full text at PMC Publisher
In one paragraph

Article in Advanced materials (Deerfield Beach, Fla.), 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 1 paper.

0numbers the graph read from it
0cells of the map it votes in
1citing papers in PubMed
–field-weighted citation impact
1 · What the graph read from it

What it found

Each row is one number read from the abstract, on the scale the paper reported it, with its interval. Left of the dashed line favours the treatment, right favours the comparator. Under each row is the sentence it came from. New to these charts? A ten-minute tutorial.

The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.

2 · The registry

The trial behind it

Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.

Neither the registry nor the abstract names a trial number. If this is a trial report, that itself is worth knowing.

3 · Its place in the literature

Who cites it

1 citing paper in PubMed.

  1. Article
4 · The record

Corrections and comments

PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.

5 · Who and what money

Authors and funding

13 authors.

Kunhee SonDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Jea Min ChoDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Dong Hoon ShinDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Yeong Rok KimDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Néstor GhenziDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Sunwoo CheongDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Byeong Su KimDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Jung Kyu LeeDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Sungho KimDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Wonho ChoiDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Soo Hyung LeeDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Janguk HanDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.
Cheol Seong HwangDepartment of Materials Science and Engineering and Inter-university Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.ORCID https://orcid.org/0000-0002-6254-9758

Funding

National Research Foundation of Korea 2020R1A3B2079882
6 · The paper itself

Abstract

Logic-in-memory (LIM) architectures are explored to address the data transfer bottleneck of conventional von Neumann architectures by integrating computation directly within memory arrays. Among various candidates, memristor-based LIM systems have gained significant attention due to their non-volatile switching behavior and compatibility with dense integration. In this work, a page-wise LIM architecture is implemented using a 3D vertical resistive random-access memory array composed of self-rectifying Pt-Ta

Indexed as

arithmetic logic unitlogic‐in‐memorymemristive logicself‐rectifying memristorvertical memristor

Identifiers

PMID41287258
PMCPMC12878806

What OpenQuestion holds

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Registered trials

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Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.