ArticleAdvanced materials (Deerfield Beach, Fla.)2026
High-Performance Air-Stable Polymer Monolayer Transistors for Monolithic 3D CMOS logics.
Article in Advanced materials (Deerfield Beach, Fla.), 2026. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 3 papers.
What it found
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
The trial behind it
Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.
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Who cites it
3 citing papers in PubMed.
- Wafer-Scale 3D Integration for High-Density Multi-Valued Neuromorphic Logic.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2026Article
- High-Performance Air-Stable Polymer Monolayer Transistors for Monolithic 3D CMOS logics.Advanced materials (Deerfield Beach, Fla.) · 2026Article
- Multi- and All-Acceptor Polymers for High-Performance n-Type Polymer Field Effect Transistors.Polymers · 2025Review
Corrections and comments
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Authors and funding
14 authors.
Funding
Abstract
The monolayer transistor, where the semiconductor layer is a single molecular layer, offers an ideal platform for exploring transport mechanisms both theoretically and experimentally by eliminating the influence of spatially correlated microstructure. However, the structure-property relations in polymer monolayers remain poorly understood, leading to low transistor performance to date. Herein, a self-confinement effect is demonstrated in the polymer monolayer with nanofibrillar microstructures and edge-on orientation, as characterized by the 4D scanning confocal electron diffraction method. The polymer chains align parallel to the nanofiber long axis, while the π-stacking direction aligns perpendicular to this axis. To reduce the trap density at the semiconductor/dielectric interface, a top-gate configuration is employed with CYTOP as gate dielectric, and the resulting monolayer transistors achieve a field-effect mobility of 7.12 cm
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Registered trials
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