Evidence map›Paper›PMID 40847772›Full record

ArticleAdvanced science (Weinheim, Baden-Wurttemberg, Germany)2025

Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next-Generation High-Density Storage Systems.

Giuk Kim, Sangho Lee, Hyojun Choi, Yangjin Jung, Woongjin Kim, Sanghyun Park, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha and 3 more

Abstract read
PubMed Full text at PMC Publisher
In one paragraph

Article in Advanced science (Weinheim, Baden-Wurttemberg, Germany), 2025. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 1 paper.

0numbers the graph read from it
0cells of the map it votes in
1citing papers in PubMed
–field-weighted citation impact
1 · What the graph read from it

What it found

Each row is one number read from the abstract, on the scale the paper reported it, with its interval. Left of the dashed line favours the treatment, right favours the comparator. Under each row is the sentence it came from. New to these charts? A ten-minute tutorial.

The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.

2 · The registry

The trial behind it

Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.

Neither the registry nor the abstract names a trial number. If this is a trial report, that itself is worth knowing.

3 · Its place in the literature

Who cites it

1 citing paper in PubMed.

  1. Article
4 · The record

Corrections and comments

PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.

5 · Who and what money

Authors and funding

13 authors.

Giuk KimDepartment of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.
Sangho LeeDepartment of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.
Hyojun ChoiDepartment of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.
Yangjin JungDepartment of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.
Woongjin KimDepartment of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.
Sanghyun ParkSemiconductor R&D Center, Samsung Electronics, Hwaseong-si, 18367, South Korea.
Kwangyou SeoSemiconductor R&D Center, Samsung Electronics, Hwaseong-si, 18367, South Korea.
Kwangsoo KimSemiconductor R&D Center, Samsung Electronics, Hwaseong-si, 18367, South Korea.
Wanki KimSemiconductor R&D Center, Samsung Electronics, Hwaseong-si, 18367, South Korea.
Daewon HaSemiconductor R&D Center, Samsung Electronics, Hwaseong-si, 18367, South Korea.
Mincheol ShinDepartment of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.
Jinho AhnDepartment of Material Science Engineering, Hanyang University, Seoul, 04763, South Korea.
Sanghun JeonDepartment of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.

Funding

Ministry of Science and ICT, South Korea RS-2023-00260527Ministry of Trade, Industry and Energy, South Korea 1415187390,00231985,23005-30FCMinistry of Trade, Industry and Energy, South Korea 1415187675,00235655,23006-15TCMinistry of Trade, Industry and Energy, South Korea 2410000582,00406007,24051-15TCSamsung Electronics Co., Ltd IO241203-11376-01
6 · The paper itself

Abstract

Multilevel storage and low-voltage operation position ferroelectric transistors as promising candidates for next-generation nonvolatile memory. Among them, gate-injection-type ferroelectric transistors offer improved vertical scalability and power efficiency for three-dimensional (3D) NAND flash. However, their intricate interplay between polarization switching and charge trapping complicates systematic understanding of degradation mechanisms, limiting strategies to improve reliability and stability. Here, gate stack engineering incorporating middle interlayers within HfZrO

Indexed as

charge‐trap‐flashferroelectricsmemory deviceNAND flashpolarization

Identifiers

PMID40847772
PMCPMC12561253

What OpenQuestion holds

Textmetadata
LicenceCC BY
Read underepoch 390

Registered trials

None linked

Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.