ArticleACS nano2025
A Versatile Top-Down Patterning Technique for Perovskite On-Chip Integration.
Article in ACS nano, 2025. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 4 papers.
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Who cites it
4 citing papers in PubMed.
- Shaping perovskite materials into micro/nanostructures for photonics and optoelectronic applications.Chemical Society reviews · 2026Review
- Precisely Printing Perovskite Nanocrystals in Glass via Thermoelectric Synergistic Effect.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2026Article
- Patterning of Lead Halide Perovskite Device Stacks on CMOS Readout Using Selective Microfabrication Protocols.Advanced materials (Deerfield Beach, Fla.) · 2026Article
- Sputtering yield for metal halide perovskite devices patterning.Science and technology of advanced materials · 2026Article
Corrections and comments
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Authors and funding
16 authors.
Funding
No grant is acknowledged in the PubMed record.
Abstract
Metal-halide perovskites (MHPs) have exciting optoelectronic properties and are under investigation for various applications, such as photovoltaics, light-emitting diodes, and lasers. An essential step toward exploiting the full potential of this class of materials is their large-scale, on-chip integration with high-resolution, top-down patterning. The development of such patterning methods for perovskite films is challenging because of their intrinsic ionic nature and adverse reactions with the solvents used in standard lithography processes. Here, we introduce a versatile and precise method comprising photolithography and reactive ion etching (RIE) processes that can be tuned to accommodate different perovskite compositions and morphologies. Our method utilizes conventional photoresists at reduced temperatures to create micron-sized features down to 1 μm, providing high reproducibility from chip to chip. The patterning technique is validated through atomic force microscopy (AFM), X-ray diffraction (XRD), optical spectroscopy, and scanning electron microscopy (SEM). It enables the scalable and high-throughput on-chip monolithic integration of MHPs.
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Registered trials
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