ArticleACS nano2025
Vertical Stacking of Atomic-Layer-Deposited Oxide Layers via a Fluorinated Graphene Transfer Technique.
Article in ACS nano, 2025. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 1 paper.
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
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Who cites it
1 citing paper in PubMed.
- Gate dielectric stack design for 2D materials-based electronics.Nano convergence · 2026Review
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10 authors.
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No grant is acknowledged in the PubMed record.
Abstract
Monolithic three-dimensional (M3D) integration of semiconductor devices offers a distinct advantage over two-dimensional size scaling by achieving higher connection densities between the device layers. Still, it presents several technological challenges, including the fabrication of upper layers, where lattice mismatch complicates the deposition of high-quality oxide layers directly onto prefabricated devices. Additionally, high-temperature postprocesses can lead to intermixing and degradation of underlying layers. Here, we demonstrate a fluorinated graphene (FG) transfer technique that enables the integration of atomic-layer-deposited oxide semiconductors and dielectrics, overcoming lattice mismatch and minimizing intermixing. The dipole interaction between fluorine and carbon in FG enables the deposition of ultraflat and high-quality oxide thin films via atomic layer deposition (ALD). Upon heating to 400 °C, the dissociation of fluorine atoms from graphene (Gr) facilitates detachment and transfer of the oxide films. Using the FG transfer method, we fabricated multiple stacks of oxide thin films with clean van der Waals interfaces, effectively preventing intermixing during the postannealing process. Furthermore, we fabricated top-gate field-effect transistors (FETs) with MoS
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