ArticleScience advances2025
Fully memristive spiking neural network for energy-efficient graph learning.
Article in Science advances, 2025. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 4 papers.
What it found
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
The trial behind it
Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.
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Who cites it
4 citing papers in PubMed.
- Neuromorphic Devices and Computing for Sensing, Memory, and Control.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2026Review
- Artificial sparse neuron dendrites for visual information inference.Science advances · 2026Article
- HfOScience advances · 2026Article
- Ultrahigh-density nested polar nanovortices with independently controllable conduction for ferroelectric memristor.Science advances · 2025Article
Corrections and comments
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Authors and funding
15 authors.
Funding
No grant is acknowledged in the PubMed record.
Abstract
Parallel and energy-efficient searching of the shortest paths on a large graph is challenging. Conventional methods commonly used are sequential and computing intensive, rendering them inadequate for addressing large-scale and real-time situations. Here, we propose a highly parallel, computation- and energy-efficient approach to shortest path-based graph learning based on an emerging memristor spiking neural network via algorithm-device codesign. The shortest path is obtained parallelly in nature using simultaneous spike traveling instead of arithmetic calculation, achieving extremely low time and space complexity. A nonlinear weight mapping approach is proposed to counterbalance the neuron intrinsic nonlinearity to guarantee accuracy to support large-scale graphs. The memristor hardware capability is experimentally demonstrated in unsupervised and supervised classification tasks. The estimated energy efficiency of 517.82 giga-traversal edges per second per watt outperforms field programmable gate arrays by three to four orders of magnitude, providing a pathway toward highly energy-efficient graph computing hardware.
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Registered trials
Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.