ArticleACS applied electronic materials2025
Miniaturized Micrometer-Level Copper Wiring and Electrodes Based on Reverse-Offset Printing for Flexible Circuits.
Article in ACS applied electronic materials, 2025. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 3 papers.
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Who cites it
3 citing papers in PubMed.
- Biobased Polymers in Printed Electronics: From Renewable Resources to Functional Devices.Polymers · 2026Review
- Low-Temperature, Sustainable Manufacturing of Printed OTFT Backplanes for Electrophoretic and OLED Displays.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2026Article
- ALD-Grown ZnO TFTs Patterned by High-Resolution Reverse-Offset Printing.ACS applied materials & interfaces · 2025Article
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Authors and funding
6 authors.
Funding
No grant is acknowledged in the PubMed record.
Abstract
High-resolution reverse-offset printing (ROP) is developed for miniaturization of printed electronics, resulting in a notable decrease in material usage compared to conventional printing processes. Two alternative ROP processes for patterning of metal conductors are available that are comparable in their cost per sample: direct nanoparticle (NP) printing (e.g., Ag and Cu) and patterning of vacuum-deposited metal (Ag, Al, Au, Cu, Ti, etc.) films using ROP printed polymer resist ink and the lift-off (LO) process. In this work, we focus on ROP of Cu NP ink followed by intense pulsed light (IPL) sintering and vacuum-deposited Cu patterned by ROP lift-off (LO). The good large-scale uniformity of the two processes is demonstrated by a grid of 300 individual thickness, sheet resistance, and resistivity measurement points with low variation over the 10 cm × 10 cm printed sample area. Sheet resistances of 0.56 ± 0.03 and 1.23 ± 0.05 Ω/□ are obtained at 113 and 40 nm thickness for Cu NP and Cu LO, respectively. Both processes show <5% thickness variation over a large area. A line-space (L/S) resolution of 2 μm is obtained for ROP patterned vacuum-deposited Cu having very low line edge roughness (LER) (∼60 nm), whereas for direct ROP printed Cu NP ink, the L/S resolution (2-4 μm) is limited by LER (∼900 nm) and influenced by the printed layer thickness. Based on the two fabrication routes, a flexible chip component assembly process is presented. Preliminary bending resistance results indicate that both ROP-based patterning processes yield a robust electrical interconnection between the ultrathin polyimide (PI) 5 mm × 5 mm chip and thermoplastic polyurethane (TPU). ROP shows promise as a scalable and sustainable patterning method for flexible ICs/chips that are assembled on flexible, stretchable, or biodegradable substrates and used, e.g., in wearable, large-scale sensing, and in environmental monitoring.
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Registered trials
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