ArticleAdvanced science (Weinheim, Baden-Wurttemberg, Germany)2025
Development of Self-Aligned Top-Gate Transistor Arrays on Wafer-Scale Two-Dimensional Semiconductor.
Article in Advanced science (Weinheim, Baden-Wurttemberg, Germany), 2025. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 2 papers.
What it found
Each row is one number read from the abstract, on the scale the paper reported it, with its interval. Left of the dashed line favours the treatment, right favours the comparator. Under each row is the sentence it came from. New to these charts? A ten-minute tutorial.
The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
The trial behind it
Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.
Neither the registry nor the abstract names a trial number. If this is a trial report, that itself is worth knowing.
Who cites it
2 citing papers in PubMed.
- Impact of Contact Gating on Scaling of Monolayer 2D Transistors Using a Symmetric Dual-Gate Structure.ACS nano · 2026Article
- Development of Self-Aligned Top-Gate Transistor Arrays on Wafer-Scale Two-Dimensional Semiconductor.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2025Article
Corrections and comments
PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.
Authors and funding
27 authors.
Funding
Abstract
Two-dimensional semiconductor materials (2DSM) effectively mitigate the short-channel effect due to their atomic thickness, offering significant advantages over traditional silicon-based materials, particularly in short channel length. In manufacturing 2DSM top-gate field-effect transistors (TG-FETs), simultaneous miniaturization of the gate and channel can only be achieved through a self-alignment process, enabling high-density integration of short-channel FETs. However, current self-aligned FETs based on 2DSM face challenges in attaining wafer-scale integration due to manufacturing process limitations. This work has successfully developed high-performance and wafer-scale TG-FET arrays using a self-aligned method that integrates the processes of dry etching, wet selective etching, and post-device optimization. The miniaturization is demonstrated by fabricating TG-FETs with a channel length of 200 nm, achieving an impressive on-state current density of 465.5 µA µm
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Registered trials
Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.