ArticleHeliyon2024
Novel parallel inputs shift registers with
Article in Heliyon, 2024. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 1 paper.
What it found
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
The trial behind it
Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.
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Who cites it
1 citing paper in PubMed.
Corrections and comments
PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.
Authors and funding
3 authors.
Funding
No grant is acknowledged in the PubMed record.
Abstract
This paper was focused on logic gates, D-latch, parallel-parallel shift-registers, and parallel-series shift registers, which are used as basic circuits in numerous circuits as well as computational and comparative units. To design proposed shift registers, D-latch which is the vital gate, is designed carefully for minimum size, decreasing number of cells and good performance for delay. The proposed level-sensitive parallel-in parallel-out (
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Registered trials
Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.