ArticleMicromachines2024
Study of Weight Quantization Associations over a Weight Range for Application in Memristor Devices.
Article in Micromachines, 2024. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 2 papers.
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2 citing papers in PubMed.
- Tunable Hydrogen Dynamics Under Electrical Bias for Neuromorphic Memory Applications.ACS applied materials & interfaces · 2026Article
- Editorial for the Special Issue on Thin Film Microelectronic Devices and Circuits.Micromachines · 2025Article
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Authors and funding
9 authors.
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Abstract
The development of hardware-based cognitive computing systems critically hinges upon the integration of memristor devices capable of versatile weight expression across a spectrum of resistance levels while preserving consistent electrical properties. This investigation aims to explore the practical implementation of a digit recognition system utilizing memristor devices with minimized weighting levels. Through the process of weight quantization for digits represented by 25 or 49 input signals, the study endeavors to ascertain the feasibility of digit recognition via neural network computation. The integration of memristor devices into the system architecture is poised to streamline the representation of the resistors required for weight expression, thereby facilitating the realization of neural-network-based cognitive systems. To minimize the information corruption in the system caused by weight quantization, we introduce the concept of "weight range" in this work. The weight range is the range between the maximum and minimum values of the weights in the neural network. We found that this has a direct impact on weight quantization, which reduces the number of digits represented by a weight below a certain level. This was found to help maintain the information integrity of the entire system despite the reduction in weight levels. Moreover, to validate the efficacy of the proposed methodology, quantized weights are systematically applied to an array of double-layer neural networks. This validation process involves the construction of cross-point array circuits with dimensions of 25 × 10 and 10 × 10, followed by a meticulous examination of the resultant changes in the recognition rate of randomly generated numbers through device simulations. Such endeavors contribute to advancing the understanding and practical implementation of hardware-based cognitive computing systems leveraging memristor devices and weight quantization techniques.
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