Implementation and optimization of SpMV algorithm based on SW26010P many-core processor and stored in BCSR format.

Mengfei Ma, Xianqing Huang, Jiali Xu, Dongning Jia

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Article in Scientific reports, 2024. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.

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4 authors.

Mengfei MaInformation Research Department, Qingdao Marine Science and Technology Center, Qingdao, China.

Xianqing HuangInformation Research Department, Qingdao Marine Science and Technology Center, Qingdao, China. xqhuang0816@163.com.

Jiali XuInformation Research Department, Qingdao Marine Science and Technology Center, Qingdao, China.

Dongning JiaCollege of Information Science and Engineering, Ocean University of China, Qingdao, China.

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6 · The paper itself

Abstract

The irregular distribution of non-zero elements of large-scale sparse matrix leads to low data access efficiency caused by the unique architecture of the Sunway many-core processor, which brings great challenges to the efficient implementation of sparse matrix-vector multiplication (SpMV) computing by SW26010P many-core processor. To address this problem, a study of SpMV optimization strategies is carried out based on the SW26010P many-core processor. Firstly, we design a memorized data storage transformation strategy to transform the matrix in CSR storage format into BCSR (Block Compressed Sparse Row) storage. Secondly, the dynamic task scheduling method is introduced to the algorithm to realize the load balance between slave cores. Thirdly, the LDM memory is refined and designed, and the slave core dual cache strategy is optimized to further improve the performance. Finally, we selected a large number of representative sparse matrices from the Matrix Market for testing. The results show that the scheme has obviously speedup the processing procedure of sparse matrices with various sizes and sizes, and the master-slave speedup ratio can reach up to 38 times. The optimization method used in this paper has implications for other complex applications of the SW26010P many-core processor.

Indexed as

Block compressed sparse rowCaching algorithmHigh performance computingSparse matrix–vector multiplicationSW26010P

Identifiers

PMID39020056

DOI10.1038/s41598-024-67462-3

PMCPMC11255231

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