ArticleScience advances2024
Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors.
Article in Science advances, 2024. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 7 papers.
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Who cites it
7 citing papers in PubMed.
- Creation of ferroelectric flux-closure transistor array for non-volatile field-effect memory.Nature communications · 2026Article
- Coupled ferroelectric-anisotropic optoelectronic synapse for polarization-sensitive neuromorphic vision.Nature communications · 2026Article
- Role of the channel on the memory window of HfZrOScientific reports · 2025Article
- Article
- Environmental Control of Ferroelectricity in Hafnia Films.Advanced materials (Deerfield Beach, Fla.) · 2025Article
- Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next-Generation High-Density Storage Systems.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2025Article
- Low-power edge detection based on ferroelectric field-effect transistor.Nature communications · 2025Article
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Authors and funding
2 authors.
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Abstract
Ferroelectric transistors based on hafnia-based ferroelectrics exhibit tremendous potential as next-generation memories owing to their high-speed operation and low power consumption. Nevertheless, these transistors face limitations in terms of memory window, which directly affects their ability to support multilevel characteristics in memory devices. Furthermore, the absence of an efficient operational technique capable of achieving multilevel characteristics has hindered their development. To address these challenges, we present a gate stack engineering method and an efficient operational approach for ferroelectric transistors to achieve 16-level data per cell operation. By using the suggested engineering method, we demonstrate the attainment of a substantial memory window of 10 V without increasing the device area. Additionally, we propose a displacement current control method, facilitating one-shot programming to the desired state. Remarkably, we suggest the compatibility of these proposed methods with three-dimensional (3D) structures. This study underscores the potential of ferroelectric transistors for next-generation 3D memory applications.
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Registered trials
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