ArticleScientific reports2024
Low power nanoscale S-FED based single ended sense amplifier applied in integrate and fire neuron circuit.
Article in Scientific reports, 2024. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
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Abstract
Current advancements in neuromorphic computing systems are focused on decreasing power consumption and enriching computational functions. Correspondingly, state-of-the-art system-on-chip developers are encouraged to design nanoscale devices with minimum power dissipation and high-speed operation. This paper deals with designing a sense amplifier based on side-contacted field-effect diodes to reduce the power-delay product (PDP) and the noise susceptibility, as critical factors in neuron circuits. Our findings reveal that both static and dynamic power consumption of the S-FED-based sense amplifier, equal to 1.86 μW and 1.92 fW/GHz, are × 243.03 and × 332.83 lower than those of the conventional CMOS counterpart, respectively. While the sense-amplifier circuit based on CMOS technology undergoes an output voltage deviation of 170.97 mV, the proposed S-FED-based one enjoys a minor output deviation of 27.31 mV. Meanwhile, the superior HIGH-level and LOW-level noise margins of the S-FED-based sense amplifier to the CMOS counterparts (∆NM
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