ArticleScientific reports2024
Core-insulator embedded nanosheet field-effect transistor for suppressing device-to-device variations.
Article in Scientific reports, 2024. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
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Authors and funding
5 authors.
Funding
Abstract
Nanosheet field-effect transistors (NSFETs) have attracted considerable attention for their potential to achieve improved performance and energy efficiency compared to traditional FinFETs. Here, we present a comprehensive investigation of core-insulator-embedded nanosheet field-effect transistors (C-NSFETs), focusing on their improved performance and device-to-device (D2D) variability compared to conventional NSFETs through three-dimensional device simulations. The C-NSFETs exhibit enhanced direct-current (DC) performance, characterized by a steeper subthreshold slope and reduced off-current, indicating better gate electrostatic controllability. Furthermore, the structural design of C-NSFETs enables to demonstrate a notable resilience against D2D variations in nanosheet thickness and doping concentration. In addition, we investigate the effects of interface traps in C-NSFETs, emphasizing the importance of thermal oxidation processes in the formation of core-insulating layers to maintain optimal device performance.
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