ArticleFrontiers in neuroscience2024
Precise and low-power closed-loop neuromodulation through algorithm-integrated circuit co-design.
Article in Frontiers in neuroscience, 2024. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 4 papers.
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Who cites it
4 citing papers in PubMed.
- Clinical application of artificial intelligence technology in epilepsy.Acta epileptologica · 2026Review
- Brain-Computer Interfaces: The Dawn of a New Era in Disease Treatment.Exploration (Beijing, China) · 2026Review
- Urban environmental exposure as a factor in adaptive neuromodulation: a conceptual framework.Frontiers in human neuroscience · 2026Article
- A Comprehensive Overview of the Current Status and Advancements in Various Treatment Strategies against Epilepsy.ACS pharmacology & translational science · 2024Review
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Authors and funding
6 authors.
Funding
No grant is acknowledged in the PubMed record.
Abstract
Implantable neuromodulation devices have significantly advanced treatments for neurological disorders such as Parkinson's disease, epilepsy, and depression. Traditional open-loop devices like deep brain stimulation (DBS) and spinal cord stimulators (SCS) often lead to overstimulation and lack adaptive precision, raising safety and side-effect concerns. Next-generation closed-loop systems offer real-time monitoring and on-device diagnostics for responsive stimulation, presenting a significant advancement for treating a range of brain diseases. However, the high false alarm rates of current closed-loop technologies limit their efficacy and increase energy consumption due to unnecessary stimulations. In this study, we introduce an artificial intelligence-integrated circuit co-design that targets these issues and using an online demonstration system for closed-loop seizure prediction to showcase its effectiveness. Firstly, two neural network models are obtained with neural-network search and quantization strategies. A binary neural network is optimized for minimal computation with high sensitivity and a convolutional neural network with a false alarm rate as low as 0.1/h for false alarm rejection. Then, a dedicated low-power processor is fabricated in 55 nm technology to implement the two models. With reconfigurable design and event-driven processing feature the resulting application-specific integrated circuit (ASIC) occupies only 5mm
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