ArticleMicromachines2024
Design and Simulation of a System-in-Package Chip for Combined Navigation.
Article in Micromachines, 2024. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
What it found
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
The trial behind it
Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.
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Who cites it
0 citing papers in PubMed, 1 citations in OpenAlex.
No citing paper in PubMed yet.
Corrections and comments
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Authors and funding
3 authors at 1 institution in 1 country.
Funding
Abstract
This paper proposes a system-in-package combination navigation chip. We used wire bonding, chip stacking, surface mount, and other processes to integrate satellite navigation chips, inertial navigation chips, microprocessor chips, and separation devices. Finally, we realized the hardware requirements for combined navigation in a 20 mm × 20 mm chip. Further, we performed a multi-physics simulation analysis of the package design. For antenna signals, the insertion loss was greater than -1 dB@1 GHz and the return loss was less than -10 dB@1 GHz. The amplitude of these noises of the signal between the MCU and the IMU was approximately 20%, and the maximum value of the coupling coefficient between signal lines on the top surface was 13.4174%. The ninth mode of the power plane yielded a maximum voltage of 55 mV, and all power delivery networks had a DC voltage drop of less than 2%. The highest temperature in the microsystem was approximately 42 °C. These results show that our design performed well in terms of signal, power, and thermal performance.
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Registered trials
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