ArticleAdvanced science (Weinheim, Baden-Wurttemberg, Germany)2023
Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm.
Article in Advanced science (Weinheim, Baden-Wurttemberg, Germany), 2023. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 6 papers.
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Who cites it
6 citing papers in PubMed, 22 citations in OpenAlex.
- Update Disturbance-Resilient Analog ReRAM Crossbar Arrays for In-Memory Deep Learning Accelerators.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2026Article
- High-Performance Synapse Arrays for Neuromorphic Computing via Floating Gate-Engineered IGZO Synaptic Transistors.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2025Article
- Disturbance-Aware On-Chip Training with Mitigation Schemes for Massively Parallel Computing in Analog Deep Learning Accelerator.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2025Article
- Retention-aware zero-shifting technique for Tiki-Taka algorithm-based analog deep learning accelerator.Science advances · 2024Article
- Analog Resistive Switching Devices for Training Deep Neural Networks with the Novel Tiki-Taka Algorithm.Nano letters · 2024Article
- Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2023Article
Corrections and comments
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Authors and funding
19 authors at 4 institutions in 1 country.
Funding
Abstract
Analog in-memory computing synaptic devices are widely studied for efficient implementation of deep learning. However, synaptic devices based on resistive memory have difficulties implementing on-chip training due to the lack of means to control the amount of resistance change and large device variations. To overcome these shortcomings, silicon complementary metal-oxide semiconductor (Si-CMOS) and capacitor-based charge storage synapses are proposed, but it is difficult to obtain sufficient retention time due to Si-CMOS leakage currents, resulting in a deterioration of training accuracy. Here, a novel 6T1C synaptic device using only n-type indium gaIlium zinc oxide thin film transistor (IGZO TFT) with low leakage current and a capacitor is proposed, allowing not only linear and symmetric weight update but also sufficient retention time and parallel on-chip training operations. In addition, an efficient and realistic training algorithm to compensate for any remaining device non-idealities such as drifting references and long-term retention loss is proposed, demonstrating the importance of device-algorithm co-optimization.
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Registered trials
Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.