A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application.

Vassilis Alimisis, Georgios Gennis, Marios Gourdouparis, Christos Dimas, Paul P Sotiriadis

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Article in Sensors (Basel, Switzerland), 2023. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 1 paper.

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1citing papers in PubMed

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1 citing paper in PubMed.

AI-driven routing and layered architectures for intelligent ICT in nanosensor networked systems.iScience · 2026
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Authors and funding

5 authors.

Vassilis AlimisisDepartment of Electrical and Computer Engineering, National Technical University of Athens, 15780 Athens, Greece.

Georgios GennisDepartment of Electrical and Computer Engineering, National Technical University of Athens, 15780 Athens, Greece.

Marios GourdouparisDepartment of Electrical and Computer Engineering, National Technical University of Athens, 15780 Athens, Greece.

Christos DimasDepartment of Electrical and Computer Engineering, National Technical University of Athens, 15780 Athens, Greece.ORCID 0000-0002-8641-2414

Paul P SotiriadisDepartment of Electrical and Computer Engineering, National Technical University of Athens, 15780 Athens, Greece.

Funding

No grant is acknowledged in the PubMed record.

6 · The paper itself

Abstract

A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.6 V), the overall power consumption is 72 μW. The classifier consists of two main components, the learning and the classification blocks, both of which are based on the mathematical equations of the hardware-friendly algorithm. Based on a real-world dataset, the proposed classifier achieves only 1.4% less average accuracy than a software-based implementation of the same model. Both design procedure and all post-layout simulations are conducted in the Cadence IC Suite, in a TSMC 90 nm CMOS process.

Indexed as

analog-hardware implementationbearing fault applicationbulk-controlled circuitslow-power designsupport vector machine

Identifiers

PMID37112319

DOI10.3390/s23083978

PMCPMC10145287

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