ArticleSensors (Basel, Switzerland)2023
Near Infrared Efficiency Enhancement of Silicon Photodiodes by Integration of Metal Nanostructures Supporting Surface Plasmon Polaritrons.
Article in Sensors (Basel, Switzerland), 2023. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 1 paper.
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1 citing paper in PubMed.
- UV-Vis-NIR Broadband Dual-Mode Photodetector Based on Graphene/InP Van Der Waals Heterostructure.Sensors (Basel, Switzerland) · 2025Article
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Authors and funding
6 authors.
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No grant is acknowledged in the PubMed record.
Abstract
Recent years have witnessed a growing interest in detectors capable of detecting single photons in the near-infrared (NIR), mainly due to the emergence of new applications such as light detection and ranging (LiDAR) for, e.g., autonomous driving. A silicon single-photon avalanche diode is surely one of the most interesting and available technologies, although it yields a low efficiency due to the low absorption coefficient of Si in the NIR. Here, we aim at overcoming this limitation through the integration of complementary metal-oxide-semiconductor (CMOS) -compatible nanostructures on silicon photodetectors. Specifically, we utilize silver grating arrays supporting surface plasmons polaritons (SPPs) to superficially confine the incoming NIR photons and therefore to increase the probability of photons generating an electron-hole pair. First, the plasmonic silver array is geometrically designed using time domain simulation software to achieve maximum detector performance at 950 nm. Then, a plasmonic silver array characterized by a pitch of 535 nm, a dot width of 428 nm, and a metal thickness of 110 nm is integrated by means of the focused ion beam technique on the detector. Finally, the integrated detector is electro-optically characterized, demonstrating a QE of 13% at 950 nm, 2.2 times higher than the reference. This result suggests the realization of a silicon device capable of detecting single NIR photons, at a low cost and with compatibility with standard CMOS technology platforms.
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