ArticleNanomaterials (Basel, Switzerland)2022
Steep-Slope and Hysteresis-Free MoS
Article in Nanomaterials (Basel, Switzerland), 2022. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
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3 authors.
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Abstract
An effective way to reduce the power consumption of an integrated circuit is to introduce negative capacitance (NC) into the gate stack. Usually, negative-capacitance field-effect transistors (NCFETs) use both a negative-capacitance layer and a positive-capacitance layer as the stack gate, which is not conductive to the scaling down of devices. In this study, a steep-slope and hysteresis-free MoS
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Registered trials
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