Evidence map›Paper›PMID 36501862›Full record

ArticleSensors (Basel, Switzerland)2022

Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices.

Xvpeng Zhang, Bingqiang Liu, Yaqi Zhao, Xiaoyu Hu, Zixuan Shen, Zhaoxia Zheng, Zhenglin Liu, Kwen-Siong Chong, Guoyi Yu, Chao Wang and 1 more

Abstract read
PubMed Full text at PMC Publisher
In one paragraph

Article in Sensors (Basel, Switzerland), 2022. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 1 paper.

0numbers the graph read from it
0cells of the map it votes in
1citing papers in PubMed
–field-weighted citation impact
1 · What the graph read from it

What it found

Each row is one number read from the abstract, on the scale the paper reported it, with its interval. Left of the dashed line favours the treatment, right favours the comparator. Under each row is the sentence it came from. New to these charts? A ten-minute tutorial.

The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.

2 · The registry

The trial behind it

Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.

Neither the registry nor the abstract names a trial number. If this is a trial report, that itself is worth knowing.

3 · Its place in the literature

Who cites it

1 citing paper in PubMed.

  1. Article
4 · The record

Corrections and comments

PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.

5 · Who and what money

Authors and funding

11 authors.

Xvpeng ZhangSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.
Bingqiang LiuSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.ORCID 0000-0003-1612-1416
Yaqi ZhaoSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.
Xiaoyu HuSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.
Zixuan ShenSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.
Zhaoxia ZhengSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.
Zhenglin LiuSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.
Kwen-Siong ChongTemasek Laboratories, Nanyang Technological University, Singapore 639798, Singapore.
Guoyi YuSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.
Chao WangSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.ORCID 0000-0002-7460-7628
Xuecheng ZouSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.

Funding

Fundamental Research Funds of the Central Universities 2019KFYXJJS049National Key R&D Program of China 2019YFB1310001
6 · The paper itself

Abstract

Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((2

Indexed as

hardware securityintelligent Internet of Thingsintelligent sensors and mobile robotsreconfigurable cryptographic accelerator

Identifiers

PMID36501862
PMCPMC9739433

What OpenQuestion holds

Textmetadata
LicenceCC BY
Read underepoch 390

Registered trials

None linked

Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.