ReviewNanomaterials (Basel, Switzerland)2022
Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials.
Review in Nanomaterials (Basel, Switzerland), 2022. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 8 papers.
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Who cites it
8 citing papers in PubMed, 38 citations in OpenAlex.
- Ultra-Low Power CMOS Logic and Photodetection in WSeACS applied materials & interfaces · 2026Article
- All van der Waals Semiconducting PtSeNano letters · 2024Article
- Contacts at the Nanoscale and for Nanomaterials.Nanomaterials (Basel, Switzerland) · 2024Review
- Manipulation of the electrical and memory properties of MoSNanoscale advances · 2023Article
- A Theoretical Study of Armchair Antimonene Nanoribbons in the Presence of Uniaxial Strain Based on First-Principles Calculations.ACS applied electronic materials · 2023Article
- Nature of the Metal Insulator Transition in High-Mobility 2D_Si-MOSFETs.Nanomaterials (Basel, Switzerland) · 2023Article
- Abridging CMOS Technology.Nanomaterials (Basel, Switzerland) · 2022Article
- Application of Two-Dimensional Materials towards CMOS-Integrated Gas Sensors.Nanomaterials (Basel, Switzerland) · 2022Review
Corrections and comments
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Authors and funding
3 authors at 1 institution in 1 country.
Funding
Abstract
For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical projections and available experimental prototypes indicate great potential for 2D field effect transistors (FETs), several major challenges must be solved to realize CMOS logic circuits based on 2D materials at the wafer scale. This review discusses the most critical issues and benchmarks against the targets outlined for the 0.7 nm node in the International Roadmap for Devices and Systems scheduled for 2034. These issues are grouped into four areas; device scaling, the formation of low-resistive contacts to 2D semiconductors, gate stack design, and wafer-scale process integration. Here, we summarize recent developments in these areas and identify the most important future research questions which will have to be solved to allow for industrial adaptation of the 2D technology.
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Registered trials
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