ArticleSensors (Basel, Switzerland)2022
A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process.
Article in Sensors (Basel, Switzerland), 2022. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 1 paper.
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
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1 citing paper in PubMed, 8 citations in OpenAlex.
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Authors and funding
3 authors at 1 institution in 1 country.
Funding
Abstract
This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm2. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode−tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.
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