ArticleSensors (Basel, Switzerland)2022
A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components.
Article in Sensors (Basel, Switzerland), 2022. The graph could read no effect estimate from its abstract, so it casts no vote on the map. An erratum has been issued. Cited by 2 papers.
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
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Who cites it
2 citing papers in PubMed.
- Time-Domain ADC and Security Co-Design for SiP-Based Wireless SAW Sensor Readers.Sensors (Basel, Switzerland) · 2025Article
- Correction: Zhang et al. A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components.Sensors (Basel, Switzerland) · 2022Article
Corrections and comments
- Erratum issued
Authors and funding
7 authors.
Funding
No grant is acknowledged in the PubMed record.
Abstract
A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input-driven by the analog input and by the reference slope generated by an FPGA output buffer-is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between -0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from -0.72 to 0.78 LSB.
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Registered trials
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