Evidence map›Paper›PMID 35484111›Full record

ArticleNature communications2022

Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors.

Junhwan Choi, Changhyeon Lee, Chungryeol Lee, Hongkeun Park, Seung Min Lee, Chang-Hyun Kim, Hocheon Yoo, Sung Gap Im

Abstract read
In one paragraph

Article in Nature communications, 2022. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 20 papers.

0numbers the graph read from it
0cells of the map it votes in
20citing papers in PubMed
–field-weighted citation impact
1 · What the graph read from it

What it found

Each row is one number read from the abstract, on the scale the paper reported it, with its interval. Left of the dashed line favours the treatment, right favours the comparator. Under each row is the sentence it came from. New to these charts? A ten-minute tutorial.

The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.

2 · The registry

The trial behind it

Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.

Neither the registry nor the abstract names a trial number. If this is a trial report, that itself is worth knowing.

3 · Its place in the literature

Who cites it

20 citing papers in PubMed.

  1. Wafer-Scale 3D Integration for High-Density Multi-Valued Neuromorphic Logic.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2026
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  7. MoSAdvanced science (Weinheim, Baden-Wurttemberg, Germany) · 2025
    Article
  8. Article
  9. Article
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  12. From Printed Devices to Vertically Stacked, 3D Flexible Hybrid Systems.Advanced materials (Deerfield Beach, Fla.) · 2025
    Review
  13. Article
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  15. Article
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4 · The record

Corrections and comments

PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.

5 · Who and what money

Authors and funding

8 authors.

Junhwan Choi *Department of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea.
Changhyeon Lee *Department of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea.
Chungryeol LeeDepartment of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea.
Hongkeun ParkDepartment of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea.ORCID http://orcid.org/0000-0002-4763-4487
Seung Min LeeDepartment of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea.
Chang-Hyun KimDepartment of Electronic Engineering Gachon University 1342 Seongnam-daero, Sujeong-gu, Seongnam, Gyeonggi-do, 13120, Korea.ORCID http://orcid.org/0000-0002-7112-6335
Hocheon YooDepartment of Electronic Engineering Gachon University 1342 Seongnam-daero, Sujeong-gu, Seongnam, Gyeonggi-do, 13120, Korea. hyoo@gachon.ac.kr.ORCID http://orcid.org/0000-0003-0772-3327
Sung Gap ImDepartment of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea. sgim@kaist.ac.kr.ORCID http://orcid.org/0000-0002-2802-6398

Funding

Korea Advanced Institute of Science and Technology | KAIST Wearable Platform Material Technology Center (Wearable Platform Materials Technology Center) 2016R1A5A1009926National Research Foundation of Korea (NRF) 2020R1A2C1101647National Research Foundation of Korea (NRF) 2021R1A2B5B03001416
6 · The paper itself

Abstract

Multi-valued logic (MVL) circuits based on heterojunction transistor (HTR) have emerged as an effective strategy for high-density information processing without increasing the circuit complexity. Herein, an organic ternary logic inverter (T-inverter) is demonstrated, where a nonvolatile floating-gate flash memory is employed to control the channel conductance systematically, thus realizing the stabilized T-inverter operation. The 3-dimensional (3D) T-inverter is fabricated in a vertically stacked form based on all-dry processes, which enables the high-density integration with high device uniformity. In the flash memory, ultrathin polymer dielectrics are utilized to reduce the programming/erasing voltage as well as operating voltage. With the optimum programming state, the 3D T-inverter fulfills all the important requirements such as full-swing operation, optimum intermediate logic value (~V

Identifiers

PMID35484111
PMCPMC9051064

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Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.