ArticleBioengineering (Basel, Switzerland)2022
Nanopower Integrated Gaussian Mixture Model Classifier for Epileptic Seizure Prediction.
Article in Bioengineering (Basel, Switzerland), 2022. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 2 papers.
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
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Who cites it
2 citing papers in PubMed.
- Highly parallel and ultra-low-power probabilistic reasoning with programmable gaussian-like memory transistors.Nature communications · 2024Article
- A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application.Sensors (Basel, Switzerland) · 2023Article
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Authors and funding
6 authors.
Funding
Abstract
This paper presents a new analog front-end classification system that serves as a wake-up engine for digital back-ends, targeting embedded devices for epileptic seizure prediction. Predicting epileptic seizures is of major importance for the patient's quality of life as they can lead to paralyzation or even prove fatal. Existing solutions rely on power hungry embedded digital inference engines that typically consume several µW or even mW. To increase the embedded device's autonomy, a new approach is presented combining an analog feature extractor with an analog Gaussian mixture model-based binary classifier. The proposed classification system provides an initial, power-efficient prediction with high sensitivity to switch on the digital engine for the accurate evaluation. The classifier's circuit is chip-area efficient, operating with minimal power consumption (180 nW) at low supply voltage (0.6 V), allowing long-term continuous operation. Based on a real-world dataset, the proposed system achieves 100% sensitivity to guarantee that all seizures are predicted and good specificity (69%), resulting in significant power reduction of the digital engine and therefore the total system. The proposed classifier was designed and simulated in a TSMC 90 nm CMOS process, using the Cadence IC suite.
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Registered trials
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