ArticleBioengineering (Basel, Switzerland)2022
Noise Power Minimization in CMOS Brain-Chip Interfaces.
Article in Bioengineering (Basel, Switzerland), 2022. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Not yet cited in PubMed.
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5 authors.
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Abstract
This paper presents specific noise minimization strategies to be adopted in silicon-cell interfaces. For this objective, a complete and general model for the analog processing of the signal coming from cell-silicon junctions is presented. This model will then be described at the level of the single stages and of the fundamental parameters that characterize them (bandwidth, gain and noise). Thanks to a few design equations, it will therefore be possible to simulate the behavior of a time-division multiplexed acquisition channel, including the most relevant parameters for signal processing, such as amplification (or power of the analog signal) and noise. This model has the undoubted advantage of being particularly simple to simulate and implement, while maintaining high accuracy in estimating the signal quality (i.e., the signal-to-noise ratio, SNR). Thanks to the simulation results of the model, it will be possible to set an optimal operating point for the front-end to minimize the artifacts introduced by the time-division multiplexing (TDM) scheme and to maximize the SNR at the a-to-d converter input. The proposed results provide an SNR of 12 dB at 10 µV
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