ArticleFrontiers in artificial intelligence2021
Enabling Training of Neural Networks on Noisy Hardware.
Article in Frontiers in artificial intelligence, 2021. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 12 papers.
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12 citing papers in PubMed.
- Implementation of offset corrected AGAD algorithm on 130-nm CMOS technology-based RRAM array for analog neural network training.Science advances · 2026Article
- Error-aware probabilistic training for memristive neural networks.Nature communications · 2025Article
- Unconventional Multimodal Switching in Single-Crystalline Nanowire Channel ECRAM.Small (Weinheim an der Bergstrasse, Germany) · 2025Article
- Resistive Switching Random-Access Memory (RRAM): Applications and Requirements for Memory and Computing.Chemical reviews · 2025Review
- Disturbance-Aware On-Chip Training with Mitigation Schemes for Massively Parallel Computing in Analog Deep Learning Accelerator.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2025Article
- Fast and robust analog in-memory deep neural network training.Nature communications · 2024Article
- Retention-aware zero-shifting technique for Tiki-Taka algorithm-based analog deep learning accelerator.Science advances · 2024Article
- Analog Resistive Switching Devices for Training Deep Neural Networks with the Novel Tiki-Taka Algorithm.Nano letters · 2024Article
- A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects.Frontiers in neuroscience · 2024Review
- Gradient-free training of recurrent neural networks using random perturbations.Frontiers in neuroscience · 2024Article
- Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm.Advanced science (Weinheim, Baden-Wurttemberg, Germany) · 2023Article
- Material to system-level benchmarking of CMOS-integrated RRAM with ultra-fast switching for low power on-chip learning.Scientific reports · 2023Article
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Abstract
Deep neural networks (DNNs) are typically trained using the conventional stochastic gradient descent (SGD) algorithm. However, SGD performs poorly when applied to train networks on non-ideal analog hardware composed of resistive device arrays with non-symmetric conductance modulation characteristics. Recently we proposed a new algorithm, the Tiki-Taka algorithm, that overcomes this stringent symmetry requirement. Here we build on top of Tiki-Taka and describe a more robust algorithm that further relaxes other stringent hardware requirements. This more robust second version of the Tiki-Taka algorithm (referred to as TTv2) 1. decreases the number of device conductance states requirement from 1000s of states to only 10s of states, 2. increases the noise tolerance to the device conductance modulations by about 100x, and 3. increases the noise tolerance to the matrix-vector multiplication performed by the analog arrays by about 10x. Empirical simulation results show that TTv2 can train various neural networks close to their ideal accuracy even at extremely noisy hardware settings. TTv2 achieves these capabilities by complementing the original Tiki-Taka algorithm with lightweight and low computational complexity digital filtering operations performed outside the analog arrays. Therefore, the implementation cost of TTv2 compared to SGD and Tiki-Taka is minimal, and it maintains the usual power and speed benefits of using analog hardware for training workloads. Here we also show how to extract the neural network from the analog hardware once the training is complete for further model deployment. Similar to Bayesian model averaging, we form analog hardware compatible averages over the neural network weights derived from TTv2 iterates. This model average then can be transferred to another analog or digital hardware with notable improvements in test accuracy, transcending the trained model itself. In short, we describe an end-to-end training and model extraction technique for extremely noisy crossbar-based analog hardware that can be used to accelerate DNN training workloads and match the performance of full-precision SGD.
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