ArticleSensors (Basel, Switzerland)2021
A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits.
Article in Sensors (Basel, Switzerland), 2021. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 6 papers.
What it found
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
The trial behind it
Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.
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Who cites it
6 citing papers in PubMed.
- Neuromorphic Sensor Based on Force-Sensing Resistors.Biomimetics (Basel, Switzerland) · 2024Article
- Enhanced read resolution in reconfigurable memristive synapses for Spiking Neural Networks.Scientific reports · 2024Article
- A Compact and Low-Power SoC Design for Spiking Neural Network Based on Current Multiplier Charge Injector Synapse.Sensors (Basel, Switzerland) · 2023Article
- Optimal Architecture of Floating-Point Arithmetic for Neural Network Training Processors.Sensors (Basel, Switzerland) · 2022Article
- An overview of brain-like computing: Architecture, applications, and future trends.Frontiers in neurorobotics · 2022Review
- Deep Learning of Explainable EEG Patterns as Dynamic Spatiotemporal Clusters and Rules in a Brain-Inspired Spiking Neural Network.Sensors (Basel, Switzerland) · 2021Article
Corrections and comments
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Authors and funding
3 authors.
Funding
Abstract
To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm
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Registered trials
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