ArticleMicromachines2021
Post-Moore Memory Technology: Sneak Path Current (SPC) Phenomena on RRAM Crossbar Array and Solutions.
Article in Micromachines, 2021. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 7 papers.
What it found
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The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.
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Who cites it
7 citing papers in PubMed, 43 citations in OpenAlex.
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- Enhancing the Uniformity of a Memristor Using a Bilayer Dielectric Structure.Micromachines · 2024Article
- Editorial for the Special Issue on the Progress of Emerging Hardware Development for Post-Moore's Computing.Micromachines · 2023Article
- Statistical Simulation of the Switching Mechanism in ZnO-Based RRAM Devices.Materials (Basel, Switzerland) · 2022Article
- Analysis of Leakage Current of HfOMicromachines · 2021Article
Corrections and comments
PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.
Authors and funding
3 authors at 3 institutions in 2 countries.
Funding
No grant is acknowledged in the PubMed record.
Abstract
The sneak path current (SPC) is the inevitable issue in crossbar memory array while implementing high-density storage configuration. The crosstalks are attracting much attention, and the read accuracy in the crossbar architecture is deteriorated by the SPC. In this work, the sneak path current problem is observed and investigated by the electrical experimental measurements in the crossbar array structure with the half-read scheme. The read margin of the selected cell is improved by the bilayer stacked structure, and the sneak path current is reduced ~20% in the bilayer structure. The voltage-read stress-induced read margin degradation has also been investigated, and less voltage stress degradation is showed in bilayer structure due to the intrinsic nonlinearity. The oxide-based bilayer stacked resistive random access memory (RRAM) is presented to offer immunity toward sneak path currents in high-density memory integrations when implementing the future high-density storage and in-memory computing applications.
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Registered trials
Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.