Evidence map›Paper›PMID 33028005›Full record

ArticleMicromachines2020

A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors.

Ah-Hyoung Lee, Jihun Lee, Farah Laiwalla, Vincent Leung, Jiannan Huang, Arto Nurmikko, Yoon-Kyu Song

Abstract read
In one paragraph

Article in Micromachines, 2020. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 7 papers.

0numbers the graph read from it
0cells of the map it votes in
7citing papers in PubMed
–field-weighted citation impact
1 · What the graph read from it

What it found

Each row is one number read from the abstract, on the scale the paper reported it, with its interval. Left of the dashed line favours the treatment, right favours the comparator. Under each row is the sentence it came from. New to these charts? A ten-minute tutorial.

The abstract states no effect estimate the extractor could read, or names no intervention and outcome on the map, so this paper lights no cell and moves no belief. It is still indexed, cited and linked below.

2 · The registry

The trial behind it

Trials whose registry record cites this paper, or whose number appears in the abstract. A trial that started after this paper was published is citing it as background, not reporting it.

Neither the registry nor the abstract names a trial number. If this is a trial report, that itself is worth knowing.

3 · Its place in the literature

Who cites it

7 citing papers in PubMed.

  1. Article
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  6. Review
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4 · The record

Corrections and comments

PubMed lists nothing against this paper. Absence here is not a guarantee, only a check that was made.

5 · Who and what money

Authors and funding

7 authors.

Ah-Hyoung LeeGraduate School of Convergence Science and Technology, Seoul National University, Seoul 08826, Korea.
Jihun LeeSchool of Engineering, Brown University, Providence, RI 02912, USA.
Farah LaiwallaSchool of Engineering, Brown University, Providence, RI 02912, USA.
Vincent LeungDepartment of Electrical and Computer Engineering, Baylor University, Waco, TX 76706, USA.
Jiannan HuangDepartment of Electrical Engineering, University of California, San Diego, CA 92161, USA.
Arto NurmikkoSchool of Engineering, Brown University, Providence, RI 02912, USA.
Yoon-Kyu SongGraduate School of Convergence Science and Technology, Seoul National University, Seoul 08826, Korea.

Funding

Defense Advanced Research Projects Agency N666001-17-C-4013National Research Foundation of Korea NRF-2016M3C7A1904987
6 · The paper itself

Abstract

Implantable active electronic microchips are being developed as multinode in-body sensors and actuators. There is a need to develop high throughput microfabrication techniques applicable to complementary metal-oxide-semiconductor (CMOS)-based silicon electronics in order to process bare dies from a foundry to physiologically compatible implant ensembles. Post-processing of a miniature CMOS chip by usual methods is challenging as the typically sub-mm size small dies are hard to handle and not readily compatible with the standard microfabrication, e.g., photolithography. Here, we present a soft material-based, low chemical and mechanical stress, scalable microchip post-CMOS processing method that enables photolithography and electron-beam deposition on hundreds of micrometers scale dies. The technique builds on the use of a polydimethylsiloxane (PDMS) carrier substrate, in which the CMOS chips were embedded and precisely aligned, thereby enabling batch post-processing without complication from additional micromachining or chip treatments. We have demonstrated our technique with 650 μm × 650 μm and 280 μm × 280 μm chips, designed for electrophysiological neural recording and microstimulation implants by monolithic integration of patterned gold and PEDOT:PSS electrodes on the chips and assessed their electrical properties. The functionality of the post-processed chips was verified in saline, and ex vivo experiments using wireless power and data link, to demonstrate the recording and stimulation performance of the microscale electrode interfaces.

Indexed as

biomedical implantsBMI (brain–machine interfaces)complementary metal–oxide–semiconductor (CMOS) post-processingon-chip electrodepolydimethylsiloxane (PDMS)-assisted planarizationscalable chip integration techniquewireless

Identifiers

PMID33028005
PMCPMC7600457

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Read under generation 80e0d062 · epoch 390. Bibliography from PubMed, PubMed Central and OpenAlex; grants from NIH RePORTER; trial links from ClinicalTrials.gov; estimates, votes and beliefs from the OpenQuestion graph.