ArticleMicromachines2020
A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors.
Article in Micromachines, 2020. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 7 papers.
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Who cites it
7 citing papers in PubMed.
- Single-Die-Level MEMS Post-Processing for Prototyping CMOS-Based Neural Probes Combined with Optical Fibers for Optogenetic Neuromodulation.Micromachines · 2026Article
- Distributed implantable microchips as wireless networks for neural sensing and stimulation.Frontiers in neuroscience · 2026Review
- A method for efficient, rapid, and minimally invasive implantation of individual non-functional motes with penetrating subcellular-diameter carbon fiber electrodes into rat cortex.Frontiers in neuroscience · 2026Article
- Fabrication and Characterization of Photovoltaic Microgenerators Using the Complementary Metal Oxide Semiconductor Process.Micromachines · 2023Article
- Fabrication and Assembly Techniques for Sub-mm Battery-Free Epicortical Implants.Micromachines · 2023Article
- New Era of Electroceuticals: Clinically Driven Smart Implantable Electronic Devices Moving towards Precision Therapy.Micromachines · 2022Review
- Design and Application of MEMS-Based Hall Sensor Array for Magnetic Field Mapping.Micromachines · 2021Article
Corrections and comments
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Authors and funding
7 authors.
Funding
Abstract
Implantable active electronic microchips are being developed as multinode in-body sensors and actuators. There is a need to develop high throughput microfabrication techniques applicable to complementary metal-oxide-semiconductor (CMOS)-based silicon electronics in order to process bare dies from a foundry to physiologically compatible implant ensembles. Post-processing of a miniature CMOS chip by usual methods is challenging as the typically sub-mm size small dies are hard to handle and not readily compatible with the standard microfabrication, e.g., photolithography. Here, we present a soft material-based, low chemical and mechanical stress, scalable microchip post-CMOS processing method that enables photolithography and electron-beam deposition on hundreds of micrometers scale dies. The technique builds on the use of a polydimethylsiloxane (PDMS) carrier substrate, in which the CMOS chips were embedded and precisely aligned, thereby enabling batch post-processing without complication from additional micromachining or chip treatments. We have demonstrated our technique with 650 μm × 650 μm and 280 μm × 280 μm chips, designed for electrophysiological neural recording and microstimulation implants by monolithic integration of patterned gold and PEDOT:PSS electrodes on the chips and assessed their electrical properties. The functionality of the post-processed chips was verified in saline, and ex vivo experiments using wireless power and data link, to demonstrate the recording and stimulation performance of the microscale electrode interfaces.
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Registered trials
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