ArticleSensors (Basel, Switzerland)2020
An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction.
Article in Sensors (Basel, Switzerland), 2020. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 8 papers.
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Who cites it
8 citing papers in PubMed.
- An FPGA-Based Event-Timing Front-End for Time-Resolved Sensing with Dual-Mode Experimental Characterization.Sensors (Basel, Switzerland) · 2026Article
- Application and Comparison of FPGA-Based Carry Chain TDC and DDMTD Schemes in High-Precision Time Synchronization.Sensors (Basel, Switzerland) · 2026Article
- A Study on the Effect of Temperature Variations on FPGA-Based Multi-Channel Time-to-Digital Converters.Sensors (Basel, Switzerland) · 2023Article
- Calibration Methods for Time-to-Digital Converters.Sensors (Basel, Switzerland) · 2023Article
- A Low Temperature Coefficient Time-to-Digital Converter with 1.3 ps Resolution Implemented in a 28 nm FPGA.Sensors (Basel, Switzerland) · 2022Article
- Optical Simulation and Experimental Assessment with Time-Walk Correction of TOF-PET Detectors with Multi-Ended Readouts.Sensors (Basel, Switzerland) · 2021Article
- Electronics for Sensors.Sensors (Basel, Switzerland) · 2021Article
- A 13-Bit, 12-ps Resolution Vernier Time-to-Digital Converter Based on Dual Delay-Rings for SPAD Image Sensor.Sensors (Basel, Switzerland) · 2021Article
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Authors and funding
10 authors.
Funding
Abstract
This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA.
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