ArticleFrontiers in neuroscience2019
Digital Biologically Plausible Implementation of Binarized Neural Networks With Differential Hafnium Oxide Resistive Memory Arrays.
Article in Frontiers in neuroscience, 2019. The graph could read no effect estimate from its abstract, so it casts no vote on the map. Cited by 15 papers.
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Who cites it
15 citing papers in PubMed.
- Wafer-scale SOT-MRAM for analog crossbar array applications.Science advances · 2026Article
- A neuromorphic processor with on-chip learning for beyond-CMOS device integration.Nature communications · 2025Article
- The logarithmic memristor-based Bayesian machine.Communications engineering · 2025Article
- Hardware implementation of memristor-based artificial neural networks.Nature communications · 2024Review
- Powering AI at the edge: A robust, memristor-based binarized neural network with near-memory computing and miniaturized solar cell.Nature communications · 2024Article
- Binary Neural Networks in FPGAs: Architectures, Tool Flows and Hardware Comparisons.Sensors (Basel, Switzerland) · 2023Review
- Thermal Characterization of Conductive Filaments in Unipolar Resistive Memories.Micromachines · 2023Article
- Photonic online learning: a perspective.Nanophotonics (Berlin, Germany) · 2023Article
- Synaptic metaplasticity in binarized neural networks.Nature communications · 2021Article
- Hardware-Efficient Stochastic Binary CNN Architectures for Near-Sensor Computing.Frontiers in neuroscience · 2021Article
- Scaling Equilibrium Propagation to Deep ConvNets by Drastically Reducing Its Gradient Estimator Bias.Frontiers in neuroscience · 2021Article
- Adaptive Extreme Edge Computing for Wearable Devices.Frontiers in neuroscience · 2021Review
- Integration and Co-design of Memristive Devices and Algorithms for Artificial Intelligence.iScience · 2020Review
- Mixed-Precision Deep Learning Based on Computational Memory.Frontiers in neuroscience · 2020Article
- Stochastic computing in convolutional neural network implementation: a review.PeerJ. Computer science · 2020Article
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Authors and funding
8 authors.
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Abstract
The brain performs intelligent tasks with extremely low energy consumption. This work takes its inspiration from two strategies used by the brain to achieve this energy efficiency: the absence of separation between computing and memory functions and reliance on low-precision computation. The emergence of resistive memory technologies indeed provides an opportunity to tightly co-integrate logic and memory in hardware. In parallel, the recently proposed concept of a Binarized Neural Network, where multiplications are replaced by exclusive NOR (XNOR) logic gates, offers a way to implement artificial intelligence using very low precision computation. In this work, we therefore propose a strategy for implementing low-energy Binarized Neural Networks that employs brain-inspired concepts while retaining the energy benefits of digital electronics. We design, fabricate, and test a memory array, including periphery and sensing circuits, that is optimized for this in-memory computing scheme. Our circuit employs hafnium oxide resistive memory integrated in the back end of line of a 130-nm CMOS process, in a two-transistor, two-resistor cell, which allows the exclusive NOR operations of the neural network to be performed directly within the sense amplifiers. We show, based on extensive electrical measurements, that our design allows a reduction in the number of bit errors on the synaptic weights without the use of formal error-correcting codes. We design a whole system using this memory array. We show on standard machine learning tasks (MNIST, CIFAR-10, ImageNet, and an ECG task) that the system has inherent resilience to bit errors. We evidence that its energy consumption is attractive compared to more standard approaches and that it can use memory devices in regimes where they exhibit particularly low programming energy and high endurance. We conclude the work by discussing how it associates biologically plausible ideas with more traditional digital electronics concepts.
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